You may use the MXP library or choose to use you own. We do not charge for the MXP library which provides many of the basic image processing functions to get you started. The beauty of this solution is that you can implement your own algorithms on the fly and keep your secret sauce… secret!
No, MXP is a processor that runs compiled C/C++ code; there is no translation to HDL. Compared to C to HDL tools, MXP lets you run and change algorithms without having to synthesize and place&route the entire FPGA system.
No, MXP is a programmable co-processor that works in conjunction with an embedded processor such as a Nios II, MicroBlaze or ARM. C/C++ applications are compiled to run on the embedded processor, and the compiled program also contains instructions, which are forwarded to MXP. The MXP instructions can be inserted directly into C code using a set of provided functions or macros.
MXP code is part of the Nios/MicroBlaze instruction stream, and so can be downloaded the same way (JTAG, flash programming, etc.).
As often as you want, and you do not have to wait for the traditional long synthesis and place&route times of traditional HW design cycles.
MXP is scalable to fit in any FPGA; the smallest MXP processor (a V1 version) is roughly the size of adding one (1) additional Nios/Microblaze CPU. Depending on the size of the FPGA you can scale it up to 128 lanes (v128) in a roughly linear fashion.
Yes, MXP acts as a coprocessor to an existing Nios / Microblaze / ARM core.
MXP offers many of the same functions as DSPs (fixed point support, saturation & rounding, etc.) but does not require a separate chip from the FPGA, reducing device footprint and bill of materials.
For common media processing, scientific, and other vectorizable applications, MXP can be as fast as implementing in VHDL/Verilog. MXP will use more logic elements than a finely tuned RTL solution, but after initial application development is done, unused features of MXP can be removed to save resources.
The simulator is an optional tool for improving productivity in both design and test. Designing with the simulator allows you to quickly assess basic performance across a number of configurations and debug code all without requiring an FPGA board. The simulator also allows for regression tests to be done entirely in software, easing integration with existing test flows.
MXP saves you time by allowing you to focus on software algorithm development rather than hardware design and implementation. You’ll have software turnaround times (seconds) instead of RTL synthesis times (10s of minutes to hours).
MXP works with the existing GCC compiler tool-chain. Individual MXP instructions can be dispatched using provided functions or macros. A middleware library with useful support functions and common media processing algorithms is provided as well.
No VHDL/Verilog knowledge is required. The MXP processor IP Core can be integrated into your system by the high-level system vendor building tools (QSYS or XPS), which creates the necessary verified HDL for HW.
MXP uses a standard Avalon or AXI memory interface and so can connect to any compatible memory controller. A configurable amount of on-chip memory is used as a temporary data storage for MXP. This memory is called our scratchpad memory and is a minimum of 4kB