TinBiNN Deep Learning Overlay

TinBiNN Deep Learning Overlay – create extremely tiny and low power deep learning applications

The VectorBlox TinBiNN Deep Learning Overlay is a set of extensions to the VectorBlox ORCA RISC-V soft-core processor designed for FPGAs. It provides up to 10 times performance using extremely lightweight vector extensions and up to 80 times performance for convolution operations in deep learning networks that use binary weights. Compatible with theVectorBlox MXP™ Matrix Processor instruction set, programming is purely done in C/C++, combining high-performance with easy programmability.

MXP Matrix Processor

MXP™ Matrix Processor – the world’s first embedded supercomputer delivered as an IP Core and completely programmable in C/C++

The VectorBlox MXP™ Matrix Processor is a scalable soft-core processor designed for FPGAs. It implements classic massively parallel vector processor algorithms traditionally used in scientific super-computers. In addition to 1D vectors, the MXP™ processor also operates on 2D and 3D matrices, increasing the application kernels it can enhance. Programming is purely done in C/C++, combining high-performance with easy programmability.

  • HW – Predefined scalable processor
  • SW – C Libraries for various processes/algorithms
  • * functional simulator
  • Adding supercomputer-class vector processing instructions to Nios II allows your software programmers to easily write C programs that run at hardware speeds.
  • Loop overheads and external memory latency are virtually eliminated by dedicated loop counters and DMA.
  • No VHDL/Verilog code or experience is necessary, so software engineers do not need to have lengthy consultations with hardware engineers when translating algorithms from software to hardware.
  • Our C/C++ compiler and library system makes it very easy to use vectors in your software.
  • Get quicker design closure using in-system software execution. We provide nearly instantaneous compile and download speeds into a real FPGA board, allowing algorithm changes to be tested instantly. If the FPGA board isn’t ready, our optional MXP Functional Simulator allows immediate algorithm development, debugging, and regression testing on your PC before the hardware is ready.
  • Since no changes to the FPGA bitstream are required, you avoid tricky VHDL/Verilog coding and lengthy place-and-route iterations.
  • Scale our vector core from smaller-than-Nios II to fill-up the FPGA.

See below how our IP allows you to decouple your hardware place-and-route team from your algorithm development team for faster bitstream design closure.