The VectorBlox MXP™ Matrix Processor™ is a scalable soft-core processor designed for FPGAs. It implements classic massively parallel vector processor algorithms traditionally used in scientific super-computers. In addition to 1D vectors, the MXP™ processor also operates on 2D and 3D matrices, increasing the application kernels it can enhance. Programming is purely done in C/C++, combining high-performance with easy programmability.

The MXP™ enhances performance of standard Altera Nios II processors by 1 to 2 orders of magnitude in many applications. It is optimized to fit into a standard FPGA as a plug-in IP block. Users write standard C programs augmented with a set of optimized MXP™ specific extensions. These extensions are easy to learn and represent typical operations like vector-add or vector-multiply.

  • Accelerates time to market
  • Only need C/C++ programming skills – No RTL or HW skills required
  • Decouples HW and SW design
  • HW speeds delivered in software
  • Up to 1000x enhancement to standard Nios II implementations
  • Supports Altera Qsys integration tools
  • Enhances standard Nios II processors in all FPGA families
  • Scalable from V1 to V128 lanes
  • Predesigned logic description of the vector processor, available as a plug-in IP module
  • C compiler with MXP™ extensions and libraries
  • Optional functional simulator; run and debug MXP™ C programs on any computer system
  • Machine Vision
  • Imaging
  • Smart Camera
  • Industrial Control
  • Financial
  • Encrypted RTL
  • Functional Simulator (optional)
  • C Extensions and Libraries for MXP™
  • User Documentation
  • Sample Code

Available Formats

MXP™ Matrix Processor™ is available in the following configurations for Altera FPGAs:

Description Target FPGA Fabric Scalability
MXP-N-Fixed Altera – Nios II Custom Instructions + Avalon Fixed size, e.g. V8
MXP-N-Configurable Configurable size, e.g. V1 to V128